An activity monitor for power/performance tuning of CMOS digital circuits

Authors:
Josep Rius;José Pineda;Maurice Meijer
Affiliations:
Departament d'Enginyeria Electrònica, Universitat Politècnica de Catalunya, Barcelona, Spain;Digital Design and Test Group, Philips Research Laboratories, Eindhoven, The Netherlands;Digital Design and Test Group, Philips Research Laboratories, Eindhoven, The Netherlands
Venue:
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Year:
2005

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Abstract

The requirement to control each possible degree of freedom of digital circuits becomes a necessity in deep submicron technologies. This requires getting a set of monitors to measure each one of the parameters of interest. This paper describes a monitor fabricated in a 90nm CMOS technology which is able to estimate the circuit activity. The output of such monitor can be used as a tool to decide how to adjust the circuit working conditions to get the best power/performance circuit response. The paper presents the implementation and experimental results of a test chip including such monitor.