Getting to the bottom of deep submicron II: a global wiring paradigm
ISPD '99 Proceedings of the 1999 international symposium on Physical design
Low-string on-chip signaling techniques: effectiveness and robustness
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low-power electronics and design
Parametric timing and power macromodels for high level simulation of low-swing interconnects
Proceedings of the 2002 international symposium on Low power electronics and design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
ISQED '04 Proceedings of the 5th International Symposium on Quality Electronic Design
Technology exploration for adaptive power and frequency scaling in 90nm CMOS
Proceedings of the 2004 international symposium on Low power electronics and design
Adaptive supply voltage technique for low swing interconnects
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
A robust self-calibrating transmission scheme for on-chip networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
VLSID '06 Proceedings of the 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design
Low-power network-on-chip for high-performance SoC design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Early wire characterization for predictable network-on-chip global interconnects
Proceedings of the 2007 international workshop on System level interconnect prediction
Impact of process variations on multicore performance symmetry
Proceedings of the conference on Design, automation and test in Europe
Optimal positions of twists in global on-chip differential interconnects
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Parallel vs. serial on-chip communication
Proceedings of the 2008 international workshop on System level interconnect prediction
Proceedings of the conference on Design, automation and test in Europe
Variation tolerant NoC design by means of self-calibrating links
Proceedings of the conference on Design, automation and test in Europe
Yield-oriented evaluation methodology of network-on-chip routing implementations
SOC'09 Proceedings of the 11th international conference on System-on-chip
A new physical routing approach for robust bundled signaling on NoC links
Proceedings of the 20th symposium on Great lakes symposium on VLSI
International Journal of Embedded and Real-Time Communication Systems
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Adaptive body bias (ABB) and adaptive supply voltage (ASV) have been showed to be effective methods for post-silicon tuning of circuit properties to reduce variability. While their properties have been compared on generic combinational circuits or microprocessor circuit sub-blocks, the advent of multi-core systems is bringing a new application domain forefront. Global interconnects are evolving to complex communication channels with drivers and receivers, in an attempt to mitigate the effects of reverse scaling and reduce power. The characterization of the performance spread of these links and the exploration of effective and power-aware compensation techniques for them is becoming a key design issue. This work compares the variability compensation efficiency of ABB vs ASV when put at work in two representative link architectures of today's ICs: a traditional full-swing interconnect and a low-swing signaling scheme for low-power communication. We provide guidelines for the post-silicon variability compensation of these communication channels.