Yield-oriented evaluation methodology of network-on-chip routing implementations

Authors:
S. Rodrigo;C. Hernández;J. Flich;F. Silla;J. Duato;S. Medardoni;D. Bertozzi;A. Mejía;D. Dai
Affiliations:
Parallel Architectures Group, Universidad Politécnica de Valencia, Valencia, Spain;Parallel Architectures Group, Universidad Politécnica de Valencia, Valencia, Spain;Parallel Architectures Group, Universidad Politécnica de Valencia, Valencia, Spain;Parallel Architectures Group, Universidad Politécnica de Valencia, Valencia, Spain;Parallel Architectures Group, Universidad Politécnica de Valencia, Valencia, Spain;ENDIF, University of Ferrara, Ferrara, Italy;ENDIF, University of Ferrara, Ferrara, Italy;Intel Corporation;Intel Corporation
Venue:
SOC'09 Proceedings of the 11th international conference on System-on-chip
Year:
2009

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Abstract

Network-on-Chip technology is gaining wide popularity for the interconnection of an increasing number of processor cores on the same silicon die. However, growing process variations cause interconnect malfunction or prevent the network from working at the intended frequency, directly impacting yield and manufacturing cost. Topology agnostic routing algorithms have the potential to tolerate process variations without degrading performance. We propose a three step methodology for evaluating routing algorithms in their ability to deal with variability. Using yield enhancement and operation speed preservation as the criteria, we demonstrate how this methodology can be used to select the best design choice among several plausible combinations of routing algorithms and implementations. Also, we show how an efficient table-less routing implementation can be used to minimise the impact of variability on manufacturing and operating frequency.