A generic architecture for on-chip packet-switched interconnections
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Micronetwork-based integration for SOCs: 673
Proceedings of the 38th annual Design Automation Conference
On-chip communication architecture for OC-768 network processors
Proceedings of the 38th annual Design Automation Conference
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
Orion: a power-performance simulator for interconnection networks
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
VLSI Architecture: Past, Present, and Future
ARVLSI '99 Proceedings of the 20th Anniversary Conference on Advanced Research in VLSI
Interconnect IP Node for Future System-on-Chip Designs
DELTA '02 Proceedings of the The First IEEE International Workshop on Electronic Design, Test and Applications (DELTA '02)
A Methodology for Designing Efficient On-Chip Interconnects on Well-Behaved Communication Patterns
HPCA '03 Proceedings of the 9th International Symposium on High-Performance Computer Architecture
aSOC: A Scalable, Single-Chip Communications Architecture
PACT '00 Proceedings of the 2000 International Conference on Parallel Architectures and Compilation Techniques
SoCBUS: Switched Network on Chip for Hard Real Time Embedded Systems
IPDPS '03 Proceedings of the 17th International Symposium on Parallel and Distributed Processing
Efficient Synthesis of Networks On Chip
ICCD '03 Proceedings of the 21st International Conference on Computer Design
xpipes: a Latency Insensitive Parameterized Network-on-chip Architecture For Multi-Processor SoCs
ICCD '03 Proceedings of the 21st International Conference on Computer Design
Analyzing On-Chip Communication in a MPSoC Environment
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Bandwidth-Constrained Mapping of Cores onto NoC Architectures
Proceedings of the conference on Design, automation and test in Europe - Volume 2
×pipesCompiler: A Tool for Instantiating Application Specific Networks on Chip
Proceedings of the conference on Design, automation and test in Europe - Volume 2
SUNMAP: a tool for automatic topology selection and generation for NoCs
Proceedings of the 41st annual Design Automation Conference
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Theory of latency-insensitive design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Design, Synthesis, and Test of Networks on Chips
IEEE Design & Test
Contrasting a NoC and a traditional interconnect fabric with layout awareness
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Application specific NoC design
Proceedings of the conference on Design, automation and test in Europe: Proceedings
An integrated open framework for heterogeneous MPSoC design space exploration
Proceedings of the conference on Design, automation and test in Europe: Proceedings
A survey of research and practices of Network-on-chip
ACM Computing Surveys (CSUR)
Proceedings of the 43rd annual Design Automation Conference
Designing application-specific networks on chips with floorplan information
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Trade-offs in the Configuration of a Network on Chip for Multiple Use-Cases
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
A tool for automatic detection of deadlock in wormhole networks on chip
ACM Transactions on Design Automation of Electronic Systems (TODAES)
MLMIN: A multicore processor and parallel computer network topology for multicast
Computers and Operations Research
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
Network Simplicity for Latency Insensitive Cores
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
Synthesis of networks on chips for 3D systems on chips
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Capturing topology-level implications of link synthesis techniques for nanoscale networks-on-chip
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Proceedings of the 2nd International Conference on Simulation Tools and Techniques
Synthesis of predictable networks-on-chip-based interconnect architectures for chip multiprocessors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Comparing tightly and loosely coupled mesochronous synchronizers in a NoC switch architecture
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
NoC topology synthesis for supporting shutdown of voltage islands in SoCs
Proceedings of the 46th Annual Design Automation Conference
Proceedings of the 2nd International Workshop on Network on Chip Architectures
The Role of Back-Pressure in Implementing Latency-Insensitive Systems
Electronic Notes in Theoretical Computer Science (ENTCS)
Flexible DOR routing for virtualization of multicore chips
SOC'09 Proceedings of the 11th international conference on System-on-chip
Yield-oriented evaluation methodology of network-on-chip routing implementations
SOC'09 Proceedings of the 11th international conference on System-on-chip
A generic network interface architecture for a networked processor array (NePA)
ARCS'08 Proceedings of the 21st international conference on Architecture of computing systems
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
IEEE Transactions on Circuits and Systems II: Express Briefs
Networks on Chips: from research to products
Proceedings of the 47th Design Automation Conference
SunFloor 3D: a tool for networks on chip topology synthesis for 3D systems on chips
Proceedings of the Conference on Design, Automation and Test in Europe
aelite: a flit-synchronous network on chip with composable and predictable services
Proceedings of the Conference on Design, Automation and Test in Europe
Exploring programming model-driven QoS support for NoC-based platforms
CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Proceedings of the Third International Workshop on Network on Chip Architectures
Sunfloor 3D: a tool for networks on chip topology synthesis for 3-D systems on chips
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Mesochronous NoC technology for power-efficient GALS MPSoCs
Proceedings of the Fifth International Workshop on Interconnection Network Architecture: On-Chip, Multi-Chip
Optimizing built-in pseudo-random self-testing for network-on-chip switches
Proceedings of the 2012 Interconnection Network Architecture: On-Chip, Multi-Chip Workshop
A distributed interleaving scheme for efficient access to WideIO DRAM memory
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
International Journal of Embedded and Real-Time Communication Systems
Proceedings of the Conference on Design, Automation and Test in Europe
A complete self-testing and self-configuring NoC infrastructure for cost-effective MPSoCs
ACM Transactions on Embedded Computing Systems (TECS) - Special Section on Wireless Health Systems, On-Chip and Off-Chip Network Architectures
Designing best effort networks-on-chip to meet hard latency constraints
ACM Transactions on Embedded Computing Systems (TECS) - Special Section on Wireless Health Systems, On-Chip and Off-Chip Network Architectures
A TDM NoC supporting QoS, multicast, and fast connection set-up
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Application-Specific Network-on-Chip synthesis with flexible router Placement
Journal of Systems Architecture: the EUROMICRO Journal
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The limited scalability of current bus topologies for Systems on Chips (SoCs) dictates the adoption of Networks on Chips (NoCs) as a scalable interconnection scheme. Current SoCs are highly heterogeneous in nature, denoting homogeneous, preconfigured NoCs as inefficient drop-in alternatives. While highly parametric, fully synthesizeable (soft) NoC building blocks appear as a good match for heterogeneous MPSoC architectures, the impact of instantiation-time flexibility on performance, power and silicon cost has not been quantified yet. This work details 脳pipes Lite, a design flow for automatic generation of heterogeneous NoCs. 脳pipes Lite is based on highly customizable, high frequency and low latency NoC modules, that are fully synthesizeable. Synthesis results provide with modules that are directly comparable, if not better, than the current published state-of-the-art NoCs in terms of area, power, latency and target frequency of operation measurements.