Optimizing built-in pseudo-random self-testing for network-on-chip switches

Authors:
Simone Terenzi;Alessandro Strano;Davide Bertozzi
Affiliations:
ENDIF, University of Ferrara, Ferrara, Italy;ENDIF, University of Ferrara, Ferrara, Italy;ENDIF, University of Ferrara, Ferrara, Italy
Venue:
Proceedings of the 2012 Interconnection Network Architecture: On-Chip, Multi-Chip Workshop
Year:
2012

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Abstract

Most BIST architectures use pseudo-random test pattern generators. However, whenever this technique has been applied to on-chip interconnection networks, overly large testing latencies have been reported. On the other hand, alternative approaches either suffer from large area penalties (like scan-based testing or the use of deterministic test patterns) or poor coverage of faults in the control path (functional testing). This paper presents the optimization of a built-in self-testing framework based on pseudo-random test patterns to the microarchitecture of network-on-chip switches. As a result, fault coverage and testing latency approach those achievable with deterministic test patterns while materializing relevant area savings and enhanced flexibility.