DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
An Efficient and Deadlock-Free Network Reconfiguration Protocol
IEEE Transactions on Computers
Addressing Manufacturing Challenges with Cost-Efficient Fault Tolerant Routing
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
Designing Network On-Chip Architectures in the Nanoscale Era
Designing Network On-Chip Architectures in the Nanoscale Era
Optimizing built-in pseudo-random self-testing for network-on-chip switches
Proceedings of the 2012 Interconnection Network Architecture: On-Chip, Multi-Chip Workshop
Power efficiency of switch architecture extensions for fault tolerant NoC design
IGCC '12 Proceedings of the 2012 International Green Computing Conference (IGCC)
Methods for fault tolerance in networks-on-chip
ACM Computing Surveys (CSUR)
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The digital design convergence, together with the new usage models of mobile devices, are raising the clear need for new requirements such as flexible partitioning, runtime adaptivity, reliability. In turn, such feature-rich architectures make the testing challenge more severe. The above trend has direct implications on the design of the underlying on-chip network, which becomes not only the system integration framework, but also the control framework executing hypervisor commands, or reacting to runtime operating conditions. The ultimate challenge for the NoC is to co-design these features together, while taking advantage of cross-feature optimization opportunities. This paper takes on this challenge and illustrates the design experience of a NoC switch architecture serving as the key enabler for the next generation of reliable and reconfigurable systems.