CAS-BUS: a scalable and reconfigurable test access mechanisms for systems on a chip
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Exploiting intellectual properties with imprecise design costs for system-on-chip synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Delay Fault Testing: Choosing Between Random SIC and Random MIC Test Sequences
Journal of Electronic Testing: Theory and Applications
Application of Deterministic Logic BIST on Industrial Circuits
Journal of Electronic Testing: Theory and Applications
Enhanced Reduced Pin-Count Test for Full-Scan Design
Journal of Electronic Testing: Theory and Applications
Reusing Scan Chains for Test Pattern Decompression
Journal of Electronic Testing: Theory and Applications
CAS-BUS: A Test Access Mechanism and a Toolbox Environment for Core-Based System Chip Testing
Journal of Electronic Testing: Theory and Applications
Economics of Built-in Self-Test
IEEE Design & Test
A Ring Architecture Strategy for BIST Test Pattern Generation
Journal of Electronic Testing: Theory and Applications
Delay Fault Testing: Choosing Between Random SIC and Random MIC Test Sequences
ETW '00 Proceedings of the IEEE European Test Workshop
Application of Deterministic Logic BIST on Industrial Circuits
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Comparing Functional and Structural Tests
ITC '00 Proceedings of the 2000 IEEE International Test Conference
A Case Study on t e Implementation of t e Illinois Scan Architecture
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Enhanced Reduced Pin-Count Test for Full-Scan Design
ITC '01 Proceedings of the 2001 IEEE International Test Conference
A New Method for Concurrent Checking by Use of a 1-out-of-4 Code
IOLTW '00 Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW)
IOLTW '00 Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW)
Towards a Standard for Embedded Core Test: An Example
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Addressable Test Ports An Approach to Testing Embedded Cores
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Analysis of Test Application Time for Test Data Compression Methods Based on Compression Codes
Journal of Electronic Testing: Theory and Applications
Self-replication for reliability: bio-inspired hardware and the embryonics project
Proceedings of the 3rd conference on Computing frontiers
Self-replicating hardware for reliability: The embryonics project
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Toward a scalable test methodology for 2D-mesh Network-on-Chips
Proceedings of the conference on Design, automation and test in Europe
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Optimizing built-in pseudo-random self-testing for network-on-chip switches
Proceedings of the 2012 Interconnection Network Architecture: On-Chip, Multi-Chip Workshop
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The market-driven electronics industry never slackens. Thanks to the swift advance of semiconductor technology, companies can and continually do introduce products with more functions, higher reliability, lower costs and at shorter intervals. ICs are considered the foundation of even traditionally nonelectronic products. So cheap are they, and so widely available, that whole industries now live off integrating ever more functions into ever smaller packages, even to creating entire systems-on-a-chip. This paper describes how such chips with 100 million transistors demand a new approach to testing-complementary embedded and external test