Delay Fault Testing: Choosing Between Random SIC and Random MIC Test Sequences

  • Authors:
  • A. Virazel;R. David;P. Girard;C. Landrault;S. Pravossoudovitch

  • Affiliations:
  • Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier Université Montpellier II/CNRS, 161 rue Ada, 34392 Montpellier Cedex 5, France. virazel@lirmm.frRene.David@lag.ensieg.inpg.fr;Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier Université Montpellier II/CNRS, 161 rue Ada, 34392 Montpellier Cedex 5, France. girard@lirmm.frlandraul@lirmm.frpravo@lirmm.fr

  • Venue:
  • Journal of Electronic Testing: Theory and Applications
  • Year:
  • 2001

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Abstract

The combination of higher quality requirements and sensitivity of high performance circuits to delay defects has led to an increasing emphasis on delay testing of VLSI circuits. In this context, it has been proven that Single Input Change (SIC) test sequences are more effective than classical Multiple Input Change (MIC) test sequences when a high robust delay fault coverage is targeted. In this paper, we show that random SIC (RSIC) test sequences achieve a higher fault coverage than random MIC (RMIC) test sequences when both robust and non-robust tests are under consideration. Experimental results given in this paper are based on a software generation of RSIC test sequences that can be easily generated in this case. For a built-in self-test (BIST) purpose, hardware generated RSIC sequences have to be used. This kind of generation will be shortly discussed at the end of the paper.