An algebraic method for delay fault testing

Authors:
S. Crepaux-Motte;M. Jacomino;R. David
Affiliations:
-;-;-
Venue:
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Year:
1996

Citing 0
Cited 6

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Comparison between Random and Pseudo-Random Generation for BIST of Delay, Stuck-at and Bridging Faults

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An efficient architecture for accumulator-based test generation of SIC pairs

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IEEE Transactions on Very Large Scale Integration (VLSI) Systems

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Abstract

This paper presents an algebraic method allowing an accurate analysis of delay faults. This method is based on the fact that some input values remain constant when two successive input vectors are applied. For a transition between two input states, the output function is reduced to a function of few variables. An analysis of the reduced function allows one to obtain the delay faults which are detected by the corresponding transition. The analysis allows one to know if a fault is robustly testable or non robustly testable and validatable, or weakly verifiable: in every case the corresponding tests are obtained. An application of the results to random testing of faults allows one to observe that some non robustly testable faults are easier to detect than some robustly testable faults.