Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
Digital signal processing in VLSI
Digital signal processing in VLSI
Accumulator-Based Compaction of Test Responses
IEEE Transactions on Computers
An efficient built-in self test method for robust path delay fault testing
Journal of Electronic Testing: Theory and Applications
Arithmetic Additive Generators of Pseudo-Exhaustive Test Patterns
IEEE Transactions on Computers
BIST Pattern Generators Using Addition and Subtraction Operations
Journal of Electronic Testing: Theory and Applications - Special issue on test synthesis
Arithmetic built-in self-test for embedded systems
Arithmetic built-in self-test for embedded systems
Computer arithmetic: algorithms and hardware designs
Computer arithmetic: algorithms and hardware designs
Journal of the ACM (JACM)
Detection of Delay Faults in Memory Address Decoders
Journal of Electronic Testing: Theory and Applications
Computer Arithmetic Algorithms
Computer Arithmetic Algorithms
Accumulator-based BIST approach for stuck-open and delay fault testing
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Delay Fault Testing: Choosing Between Random SIC and Random MIC Test Sequences
ETW '00 Proceedings of the IEEE European Test Workshop
Parallel concurrent path-delay fault simulation using single-input change patterns
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Design of an Optimal Test Pattern Generator for Built-in Self Testing of Path Delay Faults
VLSID '98 Proceedings of the Eleventh International Conference on VLSI Design: VLSI for Signal Processing
An algebraic method for delay fault testing
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Test response compaction using arithmetic functions
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
An optimized BIST test pattern generator for delay testing
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
IOLTW '00 Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW)
On Using Efficient Test Sequences for BIST
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
High-Speed Parallel-Prefix VLSI Ling Adders
IEEE Transactions on Computers
IBM Journal of Research and Development
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Arithmetic built-in self-test for DSP cores
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Test responses compaction in accumulators with rotate carry adders
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Research conducted over the years has shown that the application of single input change (SIC) pairs of test patterns for sequential, i.e. stuck-open and delay fault testing is extremely efficient. In this paper, a novel architecture for the generation of SIC pairs is presented. The implementation of the proposed architecture is based on Ling adders that are commonly utilized in current data paths due to their high-operating speed. Since the timing characteristics of the adder are not modified, the presented architecture provides a practical solution for the built-in testing of circuits that contain such adders.