Digital signal processing in VLSI

Accumulator-Based Compaction of Test Responses

IEEE Transactions on Computers

Arithmetic Additive Generators of Pseudo-Exhaustive Test Patterns

IEEE Transactions on Computers

An Accumulator-Based BIST Approach for Two-Pattern Testing

Journal of Electronic Testing: Theory and Applications

Performance analysis and optimization of latency insensitive systems

Proceedings of the 37th Annual Design Automation Conference

Testing Schemes for FIR Filter Structures

IEEE Transactions on Computers

Guest Editor's Introduction: The Maturing of DSP

IEEE Micro

Merging Data Converters and DSPs for Mixed-Signal Processors

IEEE Micro

Accumulator-based BIST approach for stuck-open and delay fault testing

EDTC '95 Proceedings of the 1995 European conference on Design and Test

Parameterizable Testing Scheme for FIR Filters

ITC '97 Proceedings of the 1997 IEEE International Test Conference

Subband Filtering Scheme for Analog and Mixed-Signal Circuit Testing

ITC '99 Proceedings of the 1999 IEEE International Test Conference

Discrimination of Homographs Distorted by a Lengthy Impulsive Noise

Informatica

An efficient architecture for accumulator-based test generation of SIC pairs

Microelectronics Journal

Accumulator-based test generation for robust sequential fault testing in DSP cores in near-optimal time

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Registration and evaluation system of the physiological data

ACMOS'05 Proceedings of the 7th WSEAS international conference on Automatic control, modeling and simulation

On concurrent error location and correction of FFT networks

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

CORDIC-Based VLSI Architecture for Implementing Kaiser-Bessel Window in Real Time Spectral Analysis

Journal of Signal Processing Systems