Digital signal processing in VLSI
Digital signal processing in VLSI
Accumulator-Based Compaction of Test Responses
IEEE Transactions on Computers
Arithmetic Additive Generators of Pseudo-Exhaustive Test Patterns
IEEE Transactions on Computers
BIST Pattern Generators Using Addition and Subtraction Operations
Journal of Electronic Testing: Theory and Applications - Special issue on test synthesis
Arithmetic built-in self-test for embedded systems
Arithmetic built-in self-test for embedded systems
On the Generation of Pseudo-Deterministic Two-Patterns Test Sequence with LFSRs
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Test response compaction using arithmetic functions
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
An optimized BIST test pattern generator for delay testing
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Arithmetic built-in self-test for DSP cores
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Accumulator-based pseudo-exhaustive two-pattern generation
Journal of Systems Architecture: the EUROMICRO Journal
Recursive pseudo-exhaustive two-pattern generation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An effective two-pattern test generator for Arithmetic BIST
Computers and Electrical Engineering
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Two-pattern tests target the detection of most commonfailure mechanisms in cmos vlsi circuits, which aremodeled as stuck-open or delay faults. In this paper theAccumulator-Based Two-pattern generation (ABT) algorithm ispresented, that generates an exhaustive n-bit two-pattern testwithin exactly 2^n × (2^n − 1) + 1 clock cycles, i.e. within thetheoretically minimum time. The ABT algorithm is implementedin hardware utilizing an accumulator whose inputs are driven byeither a binary counter (counter-based implementation) or a LinearFeedback Shift Register (LFSR-based implementation). With thecounter-based implementation different modules, having differentnumber of inputs, can be efficiently tested using the samegenerator. For circuits that do not contain counters, the LFSR-based implementation can be implemented, since registers (thattypically drive the accumulator inputs into dapatapath cores) can beeasily modified to LFSRS with small increase in the hardwareoverhead. The great advantage of the presented scheme is that it canbe implemented by augmening existing datapath components, rather thanbuilding a new pattern generation structure.