Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
A Functional Approach to Efficient Fault Detection in Iterative Logic Arrays
IEEE Transactions on Computers
C-testable modified-Booth multipliers
Journal of Electronic Testing: Theory and Applications
Arithmetic built-in self-test for embedded systems
Arithmetic built-in self-test for embedded systems
An Accumulator-Based BIST Approach for Two-Pattern Testing
Journal of Electronic Testing: Theory and Applications
LFSR-Based Deterministic TPG for Two-Pattern Testing
Journal of Electronic Testing: Theory and Applications - Special Issue on the 7th ASIAN TEST SYMPOSIUM, ATS-98
Cellular Automata-Based Recursive Pseudoexhaustive Test Pattern Generator
IEEE Transactions on Computers
Exploiting deterministic TPG for path delay testing
Journal of Computer Science and Technology
BIST Test Pattern Generators for Two-Pattern Testing-Theory and Design Algorithms
IEEE Transactions on Computers
An Effective BIST Scheme for Booth Multipliers
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
An effective BIST scheme for carry-save and carry-propagate array multipliers
ATS '95 Proceedings of the 4th Asian Test Symposium
General BIST-Amenable Method of Test Generation for Iterative Logic Arrays
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
A Testable Design of Iterative Logic Arrays
IEEE Transactions on Computers
Easily Testable Iterative Systems
IEEE Transactions on Computers
Built-in test for CMOS circuits
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Cellular automata-based pseudorandom number generators for built-in self-test
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On-chip embedding mechanisms for large sets of vectors for delay test
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Recursive pseudo-exhaustive two-pattern generation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An effective two-pattern test generator for Arithmetic BIST
Computers and Electrical Engineering
| Hi-index | 0.00 |
In this paper, a novel scheme for the generation of pseudo-exhaustive two-pattern tests for combinational modules under test is presented. The proposed scheme utilizes an accumulator with 1's complement adder to generate the patterns in time equal to the theoretical minimum. Since accumulators are commonly found in current, high-speed signal processing VLSI circuits, the presented scheme may prove a practical solution for the pseudo-exhaustive testing of such circuits for delay and stuck-open faults. Comparisons of the proposed scheme with previously proposed schemes for pseudo-exhaustive two-pattern testing reveals that the proposed generator compares favorably with respect to the required hardware overhead.