Condensed Linear Feedback Shift Register (LFSR) Testing A Pseudoexhaustive Test Technique
IEEE Transactions on Computers - The MIT Press scientific computation series
Importance Sampling for Ising Computers Using One-Dimensional Cellular Automata
IEEE Transactions on Computers
Cellular automata circuits for built-in self test
IBM Journal of Research and Development
Cellular Automata-Based Signature Analysis for Built-In Self-Test
IEEE Transactions on Computers
Recursive Pseudoexhaustive Test Pattern Generation
IEEE Transactions on Computers
Theory and Applications of Cellular Automata in Cryptography
IEEE Transactions on Computers
CAA Decoder for Cellular Automata Based Byte Error Correcting Code
IEEE Transactions on Computers
Cellular automata based synthesis of easily and fully testable FSMs
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Exhaustive Test Pattern Generation Using Cyclic Codes
IEEE Transactions on Computers
Design of CAECC - Cellular Automata Based Error Correcting Code
IEEE Transactions on Computers
Analysis of complemented CA derived from linear hybrid group CA
Computers & Mathematics with Applications
Accumulator-based pseudo-exhaustive two-pattern generation
Journal of Systems Architecture: the EUROMICRO Journal
Antirandom testing: a distance-based approach
VLSI Design
Randomness quality of permuted pseudorandom binary sequences
Mathematics and Computers in Simulation
An Approach to Searching for Two-Dimensional Cellular Automata for Recognition of Handwritten Digits
MICAI '08 Proceedings of the 7th Mexican International Conference on Artificial Intelligence: Advances in Artificial Intelligence
Recursive pseudo-exhaustive two-pattern generation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper presents a recursive technique for generation of pseudoexhaustive test patterns. The scheme is optimal in the sense that the first $2^k$ vectors cover all adjacent k-bit spaces exhaustively. It requires substantially lesser hardware than the existing methods and utilizes the regular, modular, and cascadable structure of local neighborhood Cellular Automata (CA), which is ideally suited for VLSI implementation. In terms of XOR gates, this approach outperforms earlier methods by 15 to 50 percent. Moreover, test effectiveness and hardware requirements have been established analytically, rather than by simple simulation and logic minimization.