Exhaustive Generation of Bit Patterns with Applications to VLSI Self-Testing
IEEE Transactions on Computers
Verification Testing A Pseudoexhaustive Test Technique
IEEE Transactions on Computers
Logic Test Pattern Generation Using Linear Codes
IEEE Transactions on Computers
Store Address Generator with On-Line Fault-Detection Capability
IEEE Transactions on Computers
The Weighted Syndrome Sums Approach to VLSI Testing
IEEE Transactions on Computers
Exhaustive Test Pattern Generation with Constant Weight Vectors
IEEE Transactions on Computers
Iterative exhaustive pattern generation for logic testing
IBM Journal of Research and Development
Linear Feedback Shift Register Design Using Cyclic Codes
IEEE Transactions on Computers
A coordinated approach to partitioning and test pattern generation for pseudoexhaustive testing
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
A New Framework for Designing and Analyzing BIST Techniques and Zero Aliasing Compression
IEEE Transactions on Computers
Analysis of Detection Capability of Parallel Signature Analyzers
IEEE Transactions on Computers
Arithmetic Additive Generators of Pseudo-Exhaustive Test Patterns
IEEE Transactions on Computers
Cellular Automata-Based Recursive Pseudoexhaustive Test Pattern Generator
IEEE Transactions on Computers
Novel Test Pattern Generators for Pseudoexhaustive Testing
IEEE Transactions on Computers
EDCC-3 Proceedings of the Third European Dependable Computing Conference on Dependable Computing
A tree-structured LFSR synthesis scheme for pseudo-exhaustive testing of VLSI circuits
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A programmable multiple-sequence generator for BIST applications
ATS '95 Proceedings of the 4th Asian Test Symposium
Automated synthesis of pseudo-exhaustive test generator in VLSI BIST design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper presents a design technique for linear feedback shift registers that generate test patterns for pseudoexhaustive testing. This technique is applicable to any combinational network in which none of the outputs depends on all inputs. It does not rewire the original network inputs during in-circuit test pattern generation. Thus, the possibility of undetected faults on some inputs is eliminated.