Condensed Linear Feedback Shift Register (LFSR) Testing A Pseudoexhaustive Test Technique
IEEE Transactions on Computers - The MIT Press scientific computation series
Partitioning circuits for inproved testability
Proceedings of the fourth MIT conference on Advanced research in VLSI
Graph Theory with Applications to Engineering and Computer Science (Prentice Hall Series in Automatic Computation)
Logic synthesis for efficient pseudoexhaustive testability
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
An efficient partitioning strategy for pseudo-exhaustive testing
DAC '93 Proceedings of the 30th international Design Automation Conference
IEEE Transactions on Computers
Bounds on pseudoexhaustive test lengths
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In this work, we propose a circuit partitioning and test pattern generation algorithm for built-in pseudoexhaustive self-testing of VLSI circuits. The circuit partitioning process is to partition a given circuit into a set of subcircuits such that pseudoexhaustive self-testing will be possible, while the test pattern generation process is to generate the pseudoexhaustive test patterns for each subcircuit using a linear feedback shift register (LFSR). Both problems are considered and solved in the same phase and lead to an efficient and well-coordinated solution. Experiments using computer simulation have been conducted. The results demonstrate that the proposed method is very good, especially for circuits that are highly locally connected.