A coordinated approach to partitioning and test pattern generation for pseudoexhaustive testing
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
An efficient partitioning strategy for pseudo-exhaustive testing
DAC '93 Proceedings of the 30th international Design Automation Conference
Shift Register Sequences
Novel Test Pattern Generators for Pseudo-Exhaustive Testing
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Exhaustive Generation of Bit Patterns with Applications to VLSI Self-Testing
IEEE Transactions on Computers
Verification Testing A Pseudoexhaustive Test Technique
IEEE Transactions on Computers
Reconfigurable hardware for Pseudo-exhaustive test
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Novel Test Pattern Generators for Pseudoexhaustive Testing
IEEE Transactions on Computers
Recursive pseudo-exhaustive two-pattern generation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Pseudoexhaustive testing involves applying all possible input patterns to the individual output cones of a combinational circuit. Based on our new algebraic results, we have derived both generic (cone-independent) and circuit-specific (conedependent) bounds on the minimal length of a test required so that each cone in a circuit is exhaustively tested. For any circuit with five or fewer outputs, and where each output has k or fewer inputs, we show that the circuit can always be pseudoexhaustively tested with just 2k patterns. We derive a tight upper bound on pseudoexhaustive test length for a given circuit by utilizing the knowledge of the structure of the circuit output cones. Since our circuit-specific bound is sensitive to the ordering of the circuit inputs, we show how the bound can be improved by permuting these inputs.