Condensed Linear Feedback Shift Register (LFSR) Testing A Pseudoexhaustive Test Technique
IEEE Transactions on Computers - The MIT Press scientific computation series
Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
An efficient partitioning strategy for pseudo-exhaustive testing
DAC '93 Proceedings of the 30th international Design Automation Conference
Novel Test Pattern Generators for Pseudo-Exhaustive Testing
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
PEST: a tool for implementing pseudo-exhaustive self test
EURO-DAC '90 Proceedings of the conference on European design automation
Bounds on pseudoexhaustive test lengths
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Recursive pseudo-exhaustive two-pattern generation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 14.98 |
Pseudoexhaustive testing of a combinational circuit involves applying all possible input patterns to all its individual output cones. The testing ensures detection of all detectable multiple stuck-at faults in the circuit and all detectable combinational faults within individual cones. Test pattern generators based on coding theory principles are not tailored to a specific circuit as they do not utilize any structural information. They usually generate test sets that are several orders of magnitude larger than the minimum size pseudoexhaustive test set required for a specific circuit. In this paper, we describe hardware efficient test pattern generators that employ knowledge of the circuit output cone structures for generating minimal test sets. Using our techniques, we have designed generators that generate minimum size test sets for the ISCAS benchmark circuits.