Digital Systems: Hardware Organization and Design
Digital Systems: Hardware Organization and Design
A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
The Weighted Syndrome Sums Approach to VLSI Testing
IEEE Transactions on Computers
Condensed Linear Feedback Shift Register (LFSR) Testing A Pseudoexhaustive Test Technique
IEEE Transactions on Computers - The MIT Press scientific computation series
A tree-structured LFSR synthesis scheme for pseudo-exhaustive testing of VLSI circuits
ITC '98 Proceedings of the 1998 IEEE International Test Conference
An algorithmic approach to optimizing fault coverage for BIST logic synthesis
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Using BIST Control for Pattern Generation
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Pseudoexhaustive TPG with a Provably Low Number of LFSR Seeds
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Verification Testing A Pseudoexhaustive Test Technique
IEEE Transactions on Computers
Logic Test Pattern Generation Using Linear Codes
IEEE Transactions on Computers
Pseudorandom Arrays for Built-In Tests
IEEE Transactions on Computers
Iterative exhaustive pattern generation for logic testing
IBM Journal of Research and Development
Transparent memory testing for pattern sensitive faults
ITC'94 Proceedings of the 1994 international conference on Test
Spectral Fault Signatures for Single Stuck-At Faults in Combinational Networks
IEEE Transactions on Computers
Parallel pseudorandom sequences for built-in test
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
A built-in test methodology for VLSI data paths
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
Bounds on pseudoexhaustive test lengths
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Journal of Electronic Testing: Theory and Applications
Antirandom Test Vectors for BIST in Hardware/Software Systems
Fundamenta Informaticae
| Hi-index | 14.99 |
One has a shift register of length n and a collection of designated subsets of {0, 1,···, n-1}. The problem is to devise a method for feeding a string of bits into the shift register in such an order that, for each designated subset S = {k1,···, kr}, if one keeps track of the bit patterns appearing at the corresponding positions k1, ···, krof the shift r