Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
Testing semiconductor memories: theory and practice
Testing semiconductor memories: theory and practice
Using March Tests to Test SRAMs
IEEE Design & Test
Built-In Self-Diagnosis for Repairable Embedded RAMs
IEEE Design & Test
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Built-in Self Testing of Embedded Memories
IEEE Design & Test
An Improved Method for Detecting Functional Faults in Semiconductor Random Access Memories
IEEE Transactions on Computers
Exhaustive Generation of Bit Patterns with Applications to VLSI Self-Testing
IEEE Transactions on Computers
Test Procedures for a Class of Pattern-Sensitive Faults in Semiconductor Random-Access Memories
IEEE Transactions on Computers
Analysis of multibackground memory testing techniques
International Journal of Applied Mathematics and Computer Science - Computational Intelligence in Modern Control Systems
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This paper presents a new methodology for RAM testing based on PS(n,k) fault model (the k out of n pattern sensitive fault model). According to this model the contents of any memory cell which belongs to an n-bit memory block, or ability to change the contents, is influenced by the contents of any k - 1 cells from this block. This paper includes the investigation of memory testing approaches based on the transparent pseudoexhaustive testing and its approzimations by pseudorandom circular tests, which can be used for periodic and manufacturing testing and require lower hardware and time overheads than the standard approaches.