Pseudoexhaustive TPG with a Provably Low Number of LFSR Seeds

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Venue:
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Year:
2000

Citing 6
Cited 2

Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers

IEEE Transactions on Computers - Special issue on fault-tolerant computing
Shift Register Sequences

Shift Register Sequences
Exhaustive Generation of Bit Patterns with Applications to VLSI Self-Testing

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Logic Test Pattern Generation Using Linear Codes

IEEE Transactions on Computers
Gauss-elimination-based generation of multiple seed-polynomial pairs for LFSR

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
GLFSR-a new test pattern generator for built-in-self-test

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Multiple-Seed TPG Structures

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Recursive pseudo-exhaustive two-pattern generation

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

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Abstract

Linear Feedback Shift Registers (LFSRs) are the most efficient and popular pseudo-exhaustive test pattern generation (TPG) mechanism. The goal is to minimize the required test length with low hardware overhead while obtaining pseudo-exhaustive TPG. Primitive characteristic polynomials are widely used because they require only one seed but the candidate polynomials are few and our experiments show that often the pseudo-exhaustive test length is prohibitive.In this paper, we present a novel pseudo-exhaustive approach with provably low number of seeds where the characteristic polynomial is the product of a primitive and an irreducible polynomial satisfying certain conditions. Our experimental results on the ISCAS'85 benchmarks show that using the proposed method requires very low hardware overhead. The list of characteristic polynomials for pseudo-exhaustive TPGis greatly enhanced and our experiments show that pseudo-exhaustive TPG is more feasible.