On-the-Fly Reseeding: A New Reseeding Technique for Test-Per-Clock BIST
Journal of Electronic Testing: Theory and Applications
Behavioral test generation for the selection of BIST Logic
Journal of Systems Architecture: the EUROMICRO Journal - Defect and fault tolerance in VLSI Systems
Test Set Embedding Based on Phase Shifters
EDCC-4 Proceedings of the 4th European Dependable Computing Conference on Dependable Computing
A highly regular multi-phase reseeding technique for scan-based BIST
Proceedings of the 13th ACM Great Lakes symposium on VLSI
LFSR Characteristic Polynomials for Pseudo-Exhaustive TPG with Low Number of Seeds
Journal of Electronic Testing: Theory and Applications
Pseudoexhaustive TPG with a Provably Low Number of LFSR Seeds
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Scan-BIST based on transition probabilities
Proceedings of the 41st annual Design Automation Conference
Efficient Multiphase Test Set Embedding for Scan-based Testing
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
An effective two-pattern test generator for Arithmetic BIST
Computers and Electrical Engineering
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This paper presents a new and efficient strategy of pseudorandom pattern generation (PRPG) for IC testing. It uses a general programmable LFSR (P-LFSR) to offer multiple-seed and multiple-polynomial PRPG. The deterministic pattern set generated by an ATPG tool or supplied by the designers is used to guide the generation of pseudorandom patterns. A novel application of the Gauss-elimination procedure is proposed to find the seeds as well as the polynomials. With an intelligent heuristic to further utilize the essential faults, this approach becomes very efficient, even for the random pattern resistant (RPR) circuits. Experiments are conducted on the ISCAS-85 benchmarks and the full scan version of the ISCAS-89 benchmarks. For all benchmark circuits, complete fault coverage is achieved with good balance on the hardware overhead and the test lengths as compared to other schemes