Scan-BIST based on transition probabilities

Authors:
Irith Pomeranz
Affiliations:
Purdue University, W. Lafayette, IN
Venue:
Proceedings of the 41st annual Design Automation Conference
Year:
2004

Citing 14
Cited 0

Built-in test for VLSI: pseudorandom techniques

Built-in test for VLSI: pseudorandom techniques
Generation of correlated random patterns for the complete testing of synthesized multi-level circuits

DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Structured Logic Testing

Structured Logic Testing
A Tutorial on Built-in Self-Test. I. Principles

IEEE Design & Test
A Tutorial on Built-In Self-Test, Part 2: Applications

IEEE Design & Test
Altering a Pseudo-Random Bit Sequence for Scan-Based BIST

Proceedings of the IEEE International Test Conference on Test and Design Validity
Generation of Vector Patterns Through Reseeding of Multipe-Polynominal Linear Feedback Shift Registers

Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
An efficient BIST design using LFSR-ROM architecture

ATS '00 Proceedings of the 9th Asian Test Symposium
On Calculating Efficient LFSR Seeds for Built-In Self Test

ETW '99 Proceedings of the 1999 IEEE European Test Workshop
A MIXED MODE BIST SCHEME BASED ON RESEEDING OF FOLDING COUNTERS

ITC '00 Proceedings of the 2000 IEEE International Test Conference
Pseudo Random Patterns Using Markov Sources for Scan BIST

ITC '02 Proceedings of the 2002 IEEE International Test Conference
STAR-ATPG: A High Speed Test Pattern Generator for Large Scan Designs

ITC '99 Proceedings of the 1999 IEEE International Test Conference
LT-RTPG: A New Test-Per-Scan BIST TPG for Low Heat Dissipation

ITC '99 Proceedings of the 1999 IEEE International Test Conference
Gauss-elimination-based generation of multiple seed-polynomial pairs for LFSR

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Quantified Score

Hi-index	0.01

Visualization

Abstract

We demonstrate that it is possible to generate a deterministic test set that detects all the detectable single stuck-at faults in a full-scan circuit such that each test contains a small number of transitions from 0 to 1 or from 1 to 0 when considering consecutive input values. Using this result we show that built-in test-pattern generation for scan circuits can be based on transition probabilities instead of probabilities of specific bits in the test set being 0 or 1. The resulting approach associates only two parameters with every set of test vectors: an initial value and a transition probability. We demonstrate that this approach is effective in detecting all the detectable single stuck-at faults in benchmark circuits.