Using embedded FPGAs for SoC yield improvement
Proceedings of the 39th annual Design Automation Conference
A scan BIST generation method using a markov source and partial bit-fixing
Proceedings of the 40th annual Design Automation Conference
Scan-BIST based on transition probabilities
Proceedings of the 41st annual Design Automation Conference
Evolutionary Optimization of Markov Sources for Pseudo Random Scan BIST
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A seed selection procedure for LFSR-based random pattern generators
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
A BIST TPG for low power dissipation and high fault coverage
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An Optimized Seed-based Pseudo-random Test Pattern Generator: Theory and Implementation
Journal of Electronic Testing: Theory and Applications
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We propose a new pseudo-random pattern generator for scan circuits. The proposed generator uses Markov sources to capture spatial correlations between consecutivebits inside a scan chain as defined by weight sets generated using a weighted random pattern testing method. The weight set generation is based on the analysis of deterministic test sets. The BIST scheme that uses the proposed pattern generator iteratively modifies the generator behavior to obtain a full fault coverage. Experiments conducted on large benchmark circuitsdemonstrate that the proposed BIST methodology can achieve full fault coverage with a small number of tests and a small hardware overhead.