A method for generating weighted random test pattern
IBM Journal of Research and Development
Constructive Multi-Phase Test Point Insertion for Scan-Based BIST
Proceedings of the IEEE International Test Conference on Test and Design Validity
A scan BIST generation method using a markov source and partial bit-fixing
Proceedings of the 40th annual Design Automation Conference
Low Power BIST by Filtering Non-Detecting Vectors
ETW '99 Proceedings of the 1999 IEEE European Test Workshop
Test point insertion based on path tracing
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
A Test Vector Inhibiting Technique for Low Energy BIST Design
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Low Power BIST via Non-Linear Hybrid Cellular Automata
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Pseudo Random Patterns Using Markov Sources for Scan BIST
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Low Power Testing of VLSI Circuits: Problems and Solutions
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Scan BIST Targeting Transition Faults Using a Markov Source
ISQED '04 Proceedings of the 5th International Symposium on Quality Electronic Design
Evolutionary Optimization of Markov Sources for Pseudo Random Scan BIST
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
First Level Hold: A Novel Low-Overhead Delay Fault Testing Technique
DFT '04 Proceedings of the Defect and Fault Tolerance in VLSI Systems, 19th IEEE International Symposium
Low Power BIST with Smoother and Scan-Chain Reorder
ATS '04 Proceedings of the 13th Asian Test Symposium
ATS '04 Proceedings of the 13th Asian Test Symposium
Weighted Pseudo-Random BIST for N-Detection of Single Stuck-at Faults
ATS '04 Proceedings of the 13th Asian Test Symposium
Power Reduction in Test-Per-Scan BIST with Supply Gating and Efficient Scan Partitioning
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
A routability constrained scan chain ordering technique for test power reduction
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Using Weighted Scan Enable Signals to Improve Test Effectiveness of Scan-Based BIST
IEEE Transactions on Computers
A BIST TPG for low power dissipation and high fault coverage
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low-Transition Test Pattern Generation for BIST-Based Applications
IEEE Transactions on Computers
Markov source based test length optimized SCAN-BIST architecture
ISQED '09 Proceedings of the 2009 10th International Symposium on Quality of Electronic Design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Low-power scan design using first-level supply gating
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Weighted pseudorandom hybrid BIST
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low-power weighted random pattern testing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
DS-LFSR: a BIST TPG for low switching activity
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Test pattern generation and clock disabling for simultaneous test time and power reduction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A Reconfigurable Scan Architecture With Weighted Scan-Enable Signals for Deterministic BIST
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper presents a novel seed-based test pattern generator (SB-TPG). The core of SB-TPG is a seed sequence generator. A coverage-driven seed generation algorithm has been proposed to generate the optimized seeds. The test sequence generated by SB-TPG is a single input change (SIC) sequence that can significantly reduce test power for test-per-clock built-in self-test (BIST). Further, seed-masking technique has been put forward to filter those power-consuming seeds, thus reducing test power for test-per-scan BIST. Experimental results show that SB-TPG can achieve high fault coverage with short test length, low power and small hardware overhead.