A scan BIST generation method using a markov source and partial bit-fixing

Authors:
Wei Li;Chaowen Yu;Sudhakar M. Reddy;Irith Pomeranz
Affiliations:
Univ. of Iowa, Iowa City, IA;Univ. of Iowa, Iowa City, IA;Univ. of Iowa, Iowa City, IA;Purdue University, West Lafayette, IN
Venue:
Proceedings of the 40th annual Design Automation Conference
Year:
2003

Citing 9
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Abstract

Recently, Markov sources were shown to be effective in designing pseudo-random test pattern generators with low area overhead for built-in self-test of scan designs. This paper presents a new test pattern generation scheme based on a Markov source and a partial bit-fixing technique. A new method is proposed for the computation of the state transition probabilities of the Markov source based on the statistics of a deterministic test set. This is enhanced by partial bit-fixing logic, which fixes a group of consecutive inputs to all-0 or all-1. Experimental results show that the proposed BIST scheme can achieve 100% fault coverage for large benchmark circuits with reduced hardware overhead and reduced pattern counts compared to the earlier method using Markov sources.