Low hardware overhead scan based 3-weight weighted random BIST

Using embedded FPGAs for SoC yield improvement

Proceedings of the 39th annual Design Automation Conference

A Ring Architecture Strategy for BIST Test Pattern Generation

Journal of Electronic Testing: Theory and Applications

A scan BIST generation method using a markov source and partial bit-fixing

Proceedings of the 40th annual Design Automation Conference

Hybrid BIST Based on Repeating Sequences and Cluster Analysis

Proceedings of the conference on Design, Automation and Test in Europe - Volume 2

Hardware Ef.cient LBISTWith Complementary Weights

ICCD '05 Proceedings of the 2005 International Conference on Computer Design

Efficient scan-based BIST scheme for low power testing of VLSI chips

Proceedings of the 2006 international symposium on Low power electronics and design

Scan-BIST based on cluster analysis and the encoding of repeating sequences

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Using Weighted Scan Enable Signals to Improve Test Effectiveness of Scan-Based BIST

IEEE Transactions on Computers

A BIST TPG for low power dissipation and high fault coverage

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Column-matching based mixed-mode test pattern generator design technique for BIST

Microprocessors & Microsystems

A test set embedding approach based on twisted-ring counter with few seeds

Integration, the VLSI Journal

A low overhead high test compression technique using pattern clustering with n-detection test support

IEEE Transactions on Very Large Scale Integration (VLSI) Systems