Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Test set compaction algorithms for combinational circuits
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Test Data Decompression for Multiple Scan Designs with Boundary Scan
IEEE Transactions on Computers
Low hardware overhead scan based 3-weight weighted random BIST
Proceedings of the IEEE International Test Conference 2001
Two-dimensional test data compression for scan-based deterministic BIST
Proceedings of the IEEE International Test Conference 2001
Test vector encoding using partial LFSR reseeding
Proceedings of the IEEE International Test Conference 2001
Test Point Insertion for an Area Efficient BIST
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Test Data Compression Using Dictionaries with Fixed-Length Indices
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
A MIXED MODE BIST SCHEME BASED ON RESEEDING OF FOLDING COUNTERS
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Embedded Deterministic Test for Low-Cost Manufacturing Test
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Reducing Test Dat Volume Using LFSR Reseeding with Seed Compression
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Proceedings of the conference on Design, automation and test in Europe
Hybrid BIST Based on Weighted Pseudo-Random Testing: A New Test Resource Partitioning Scheme
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
IEEE Transactions on Computers
DATA COMPRESSION FOR MULTIPLE SCAN CHAINS USING DICTIONARIES WITH CORRECTIONS
ITC '04 Proceedings of the International Test Conference on International Test Conference
Cluster Analysis
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
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We present a hybrid BIST approach that extracts the most frequently occurring sequences from deterministic test patterns; these extracted sequences are stored on-chip. We use cluster analysis for sequence extraction, and encode deterministic patterns on the basis of the stored sequences. Experimental results for the ISCAS-89 benchmark circuits show that the proposed approach often requires less on-chip storage and test data volume than other recent BIST methods.