Test data compression using dictionaries with selective entries and fixed-length indices
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Analysis of Test Application Time for Test Data Compression Methods Based on Compression Codes
Journal of Electronic Testing: Theory and Applications
3-Stage Variable Length Continuous-Flow Scan Vector Decompression Scheme
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Combining dictionary coding and LFSR reseeding for test data compression
Proceedings of the 41st annual Design Automation Conference
Test Data Compression: The System Integrator's Perspective
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Test data compression technique for embedded cores using virtual scan chains
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
RL-huffman encoding for test compression and power reduction in scan applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Evolutionary Optimization in Code-Based Test Compression
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Hybrid BIST Based on Repeating Sequences and Cluster Analysis
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Journal of Electronic Testing: Theory and Applications
Test compression for scan circuits using scan polarity adjustment and pinpoint test relaxation
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
A Huffman-based coding with efficient test application
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Response shaper: a novel technique to enhance unknown tolerance for output response compaction
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Data-Independent Pattern Run-Length Compression for Testing Embedded Cores in SoCs
IEEE Transactions on Computers
Proceedings of the 18th ACM Great Lakes symposium on VLSI
A Variable-Length Coding Adjustable for Compressed Test Application
IEICE - Transactions on Information and Systems
Test Data Compression Using Multi-dimensional Pattern Run-length Codes
Journal of Electronic Testing: Theory and Applications
Journal of Electronic Testing: Theory and Applications
MICRO: a new hybrid test data compression/ decompression scheme
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Nine-coded compression technique for testing embedded cores in socs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Test data compression based on geometric shapes
Computers and Electrical Engineering
Deterministic test vector compression / decompression using an embedded processor
EDCC'05 Proceedings of the 5th European conference on Dependable Computing
Efficient Test Compression Technique for SoC Based on Block Merging and Eight Coding
Journal of Electronic Testing: Theory and Applications
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This paper proposes a new test data compression/decompression method for systems-on-a-chip. Themethod is based on analyzing the factors that influencetest parameters: compression ratio, area overhead and testapplication time. To improve compression ratio, the newmethod is based on a Variable-length Input Huffman Coding(VIHC), which fully exploits the type and length of the patterns,as well as a novel mapping and reordering algorithmproposed in a pre-processing step. The new VIHC algorithmis combined with a novel parallel on-chip decoder that simultaneouslyleads to low test application time and low areaoverhead. It is shown that, unlike three previous approaches[2, 3, 10] which reduce some test parameters at the expenseof the others, the proposed method is capable of improvingall the three parameters simultaneously. For example, theproposed method leads to similar or better compression ratiowhen compared to frequency directed run-length coding[2], however with lower area overhead and test applicationtime. Similarly, there is comparable or lower area overheadand test application time with respect to Golomb coding [3],with improvements in compression ratio. Finally, there issimilar or improved test application time when comparedto selective coding [10], with reductions in compression ratioand significantly lower area overhead. An experimentalcomparison on benchmark circuits validates the proposedmethod.