IEEE Spectrum
Test set compaction algorithms for combinational circuits
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Deterministic Built-in Pattern Generation for Sequential Circuits
Journal of Electronic Testing: Theory and Applications
Very Low Cost Testers: Opportunities and Challenges
IEEE Design & Test
Scan chain design for test time reduction in core-based ICs
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Test vector decompression via cyclical scan chains and its application to testing core-based designs
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Scan Vector Compression/Decompression Using Statistical Coding
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Test Data Compression for System-on-a-Chip Using Golomb Codes
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Deterministic Test Vector Decompression in Software Using Linear Operations
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
Multiscan-Based Test Compression and Hardware Decompression Using LZ77
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Proceedings of the conference on Design, automation and test in Europe
Test data compression using dictionaries with selective entries and fixed-length indices
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Matrix-based software test data decompression for systems-on-a-chip
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Desing and test of systems on a chip
A Technique for High Ratio LZW Compression
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
RL-huffman encoding for test compression and power reduction in scan applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Application of Arithmetic Coding to Compression of VLSI Test Data
IEEE Transactions on Computers
An Efficient Data-Independent Technique for Compressing Test Vectors in Systems-on-a-Chip
ISVLSI '06 Proceedings of the IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures
Nine-coded compression technique for testing embedded cores in socs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A unified approach to reduce SOC test data volume, scan power and testing time
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An efficient test vector compression scheme using selective Huffman coding
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Test data compression using alternating variable run-length code
Integration, the VLSI Journal
| Hi-index | 14.98 |
This paper presents a new compression technique for testing the intellectual property (IP) cores in system-on-chips. The pattern run-length compression applies the well-known run-length coding to equal and complementary consecutive patterns of the precomputed test data. No structural information of the IP cores is required by the encoding procedure. A data-independent decompressor can be realized by the embedded processor or on-chip circuitry. The decompressed test set can be flexibly applied to a single-scan or multiple-scan chain of each core-under-test. Experiments on ISCAS-89 benchmarks show that the new technique results in superior compression performance. The test application time is also significantly reduced.