Economics of design and test for electronic circuits and systems
Economics of design and test for electronic circuits and systems
Test economics and design for testability for electronic circuits and systems
Test economics and design for testability for electronic circuits and systems
DFT-Focused Chip Testers: What Can They Really Do?
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Synchronization overhead in SOC compressed test
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Concurrent Core Test for Test Cost Reduction Using Merged Test Set and Scan Tree
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Concurrent core test for SOC using shared test set and scan chain disable
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Data-Independent Pattern Run-Length Compression for Testing Embedded Cores in SoCs
IEEE Transactions on Computers
Test Data Compression for Scan-Based BIST Aiming at 100x Compression Rate
IEICE - Transactions on Information and Systems
| Hi-index | 0.00 |
Prudent application of design-for-testability guidelines can yield designs that don't require all the expensive features of traditional automated test equipment. The authors describe how the VLSI design and semiconductor test communities can cooperate to greatly reduce testing costs.