Cost and benefit models for logic and memory BIST
DATE '00 Proceedings of the conference on Design, automation and test in Europe
A detailed cost model for concurrent use with hardware/software co-design
Proceedings of the 39th annual Design Automation Conference
Analyzing Packaging Trade-Offs During System Design
IEEE Design & Test
Very Low Cost Testers: Opportunities and Challenges
IEEE Design & Test
Economics of Built-in Self-Test
IEEE Design & Test
A New Test/Diagnosis/Rework Model for Use in Technical Cost Modeling of Electronic Systems Assembly
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Hi-index | 0.00 |