Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
Test economics and design for testability for electronic circuits and systems
Test economics and design for testability for electronic circuits and systems
IEEE Spectrum
Cost and benefit models for logic and memory BIST
DATE '00 Proceedings of the conference on Design, automation and test in Europe
The Economics of System-Level Testing
IEEE Design & Test
Challenges and directions for testing IC
Integration, the VLSI Journal
A seed selection procedure for LFSR-based random pattern generators
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Test Data Compression for Scan-Based BIST Aiming at 100x Compression Rate
IEICE - Transactions on Information and Systems
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Using built-in self-test at the right level offers users significant cost savings, but determining which level, if any, is best for BIST can be complex. A detailed economic analysis can unravel heterogeneous costs and benefits so that designers and managers can make the right decision.