Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
Generation of deterministic test patterns by minimal basic test sets
EURO-DAC '92 Proceedings of the conference on European design automation
IEEE Transactions on Computers - Special issue on fault-tolerant computing
Logic partitioning to pseudo-exhaustive test for BIST design
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
System-on-a-Chip: Design and Test
System-on-a-Chip: Design and Test
Test of future system-on-chips
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Economics of Built-in Self-Test
IEEE Design & Test
Modeling the Economics of Testing: A DFT Perspective
IEEE Design & Test
MFBIST: A BIST Method for Random Pattern Resistant Circuits
Proceedings of the IEEE International Test Conference on Test and Design Validity
BIST vs. ATE: need a different vehicle?
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Novel Test Pattern Generators for Pseudo-Exhaustive Testing
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Test vector encoding using partial LFSR reseeding
Proceedings of the IEEE International Test Conference 2001
BIST vs. ATE for testing system-on-a-chip
ITC '98 Proceedings of the 1998 IEEE International Test Conference
On Chip Weighted Random Patterns
ATS '97 Proceedings of the 6th Asian Test Symposium
Pseudo-Exhaustive Testing of Sequential Circuits
GLS '99 Proceedings of the Ninth Great Lakes Symposium on VLSI
20.2 New Techniques for Deterministic Test Pattern Generation
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Pseudo-random pattern testing of bridging faults
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
IOLTW '00 Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW)
Test Support Processors for Enhanced Testability of High Performance Circuits
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Design for Test and Time to Market -- Friends or Foes
ITC '99 Proceedings of the 1999 IEEE International Test Conference
An efficient method for generating exhaustive test sets
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
GLFSR-a new test pattern generator for built-in-self-test
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
DNA computing approach for automated test pattern generation for digital circuits
International Journal of Systems Science
A New Built-in TPG Based on Berlekamp---Massey Algorithm
Journal of Electronic Testing: Theory and Applications
Challenges for Semiconductor Test Engineering: A Review Paper
Journal of Electronic Testing: Theory and Applications
Hi-index | 0.00 |
In today's semiconductor world, integration technology is improving and refining dramatically. With the continuous increase of integration densities and complexities, the problem of integrated circuit (IC) testing has become much more acute. IC testing is now no more a back-end issue, rather it has become a front-end burning issue, which needs an economic solution with reliable performance. Otherwise all the benefits of semiconductor technology would be meaningless. A roadmap of semiconductor technology in the context of IC testing is shown in this paper. Researchers and manufacturers can get to know current challenges and directions of IC testing through this discussion.