The Mutating Metric for Benchmarking Test
IEEE Design & Test
Challenges and directions for testing IC
Integration, the VLSI Journal
| Hi-index | 4.10 |
Designers can now place millions of transistors on a single chip and propagate a signal through them at speeds approaching one gigahertz. With all this progress on the design front, it's easy to overlook a simple fact: More complex designs also pose problems for manufacturing and test. The challenges are especially acute in test. Test costs traditionally rise as frequency, transistors, and pin counts increase. Without substantial changes in test technology, the billion-transistor ICs projected within the next 12 years could cost many times more to test than the 40-million-transistor microprocessors of today. Test costs today are already high. Large testers can cost up to $6 million, as each pin costs between $5,000 and $10,000. Current IC pin counts are in the hundreds. Nanometer designs are anticipated to have pin counts in the thousands. Manufacturers will continue to pay these high test equipment costs for some time because the cost of changing systems is even more staggering. Why are these costs so high and how are they affected by nanometer technologies? The authors answer these questions by looking to the defects that occur in semiconductor manufacturing. In looking at the future, the test community sees staggering challenges based on the predictions in The 1997 National Technology Roadmap for Semiconductors, including the development testers with accuracies of a few picoseconds.