Minimizing concurrent test time in SoC's by balancing resource usage
Proceedings of the 12th ACM Great Lakes symposium on VLSI
Coping with Latency in SOC Design
IEEE Micro
A Flexible Power Model for FPGAs
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Is the Die Cast for the Token Game?
ICATPN '02 Proceedings of the 23rd International Conference on Applications and Theory of Petri Nets
Fast processor core selection for WLAN modem using mappability estimation
Proceedings of the tenth international symposium on Hardware/software codesign
Vector vs. superscalar and VLIW architectures for embedded multimedia benchmarks
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
Embedded-Memory Test and Repair: Infrastructure IP for SoC Yield
IEEE Design & Test
Low-Latency Contro Structures with Slack
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
Extending Platform-Based Design to Network on Chip Systems
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
SystemC
A design methodology for NOC-based systems
Networks on chip
A parallel computer as a NOC region
Networks on chip
Single-ISA Heterogeneous Multi-Core Architectures: The Potential for Processor Power Reduction
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
A Low-Power Heterogeneous Multiprocessor Architecture for Audio Signal Processing
Journal of VLSI Signal Processing Systems
Ambient intelligence: a computational platform perspective
Ambient intelligence
Challenges and directions for testing IC
Integration, the VLSI Journal
Memory Fault Modeling Trends: A Case Study
Journal of Electronic Testing: Theory and Applications
A scalable, clustered SMT processor for digital signal processing
MEDEA '03 Proceedings of the 2003 workshop on MEmory performance: DEaling with Applications , systems and architecture
An Energy Efficient Instruction Set Synthesis Framework for Low Power Embedded System Designs
IEEE Transactions on Computers
StressTest: an automatic approach to test generation via activity monitors
Proceedings of the 42nd annual Design Automation Conference
Cluster of re-configurable nodes for scanning large genomic banks
Parallel Computing
A curriculum for embedded system engineering
ACM Transactions on Embedded Computing Systems (TECS)
Power complexity of multiplexer-based optoelectronic crossbar switches
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Deployment of Better Than Worst-Case Design: Solutions and Needs
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Low-power programmable routing circuitry for FPGAs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Depth-driven verification of simultaneous interfaces
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
COSMECA: application specific co-synthesis of memory and communication architectures for MPSoC
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Practical methods in coverage-oriented verification of the merom microprocessor
Proceedings of the 43rd annual Design Automation Conference
Combining Scan Test and Built-in Self Test
Journal of Electronic Testing: Theory and Applications
SHAPES:: a tiled scalable software hardware architecture platform for embedded systems
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Reducing leakage in power-saving capable caches for embedded systems by using a filter cache
MEDEA '07 Proceedings of the 2007 workshop on MEmory performance: DEaling with Applications, systems and architecture
Filtering drowsy instruction cache to achieve better efficiency
Proceedings of the 2008 ACM symposium on Applied computing
Journal of Signal Processing Systems - Special Issue: Embedded computing systems for DSP
Test set development for cache memory in modern microprocessors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Gating transistor power saving technique for power optimized code book SRAM
Proceedings of the International Conference on Advances in Computing, Communication and Control
Accurate Instruction Pre-scheduling in Dynamically Scheduled Processors
Transactions on High-Performance Embedded Architectures and Compilers II
Modified essential spare pivoting algorithm for embedded memories with global block-based redundancy
CSS '07 Proceedings of the Fifth IASTED International Conference on Circuits, Signals and Systems
Asynchronous Bypass Channels: Improving Performance for Multi-synchronous NoCs
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
Efficient BISR techniques for embedded memories considering cluster faults
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the Conference on Design, Automation and Test in Europe
Efficient built-in redundancy analysis for embedded memories with 2-d redundancy
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
3D floorplanning of low-power and area-efficient Network-on-Chip architecture
Microprocessors & Microsystems
GALS-Designer: A design framework for GALS software systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Synchronization fault cryptanalysis for breaking a5/1
WEA'05 Proceedings of the 4th international conference on Experimental and Efficient Algorithms
SAMOS'06 Proceedings of the 6th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
Optimized Implementation of RNS FIR Filters Based on FPGAs
Journal of Signal Processing Systems
| Hi-index | 4.10 |
The International Technology Roadmap for Semiconductors is a worldwide collaborative effort within the semiconductor industry to confront the challenges implicit in Moore's law. The Roadmap's goal is to present an industry-wide consensus on the "best current estimate" of its R&D needs out to a 15-year horizon. As such, the ITRS provides a guide to the efforts of companies, research organizations, and governments to improve the quality of R&D investment decisions made at all levels. The 2001 Roadmap is notable because it was developed with truly international representation. In this article, representatives of the International Technology Working Groups for Design and Test showcase some of the contributions from 839 international experts seeking to address the difficult and exciting challenges facing the design and test communities and the semiconductor industry as a whole.