Available instruction-level parallelism for superscalar and superpipelined machines
ASPLOS III Proceedings of the third international conference on Architectural support for programming languages and operating systems
Journal of Computer and System Sciences
An introduction to parallel algorithms
An introduction to parallel algorithms
Highly parallel computing (2nd ed.)
Highly parallel computing (2nd ed.)
Dynamic Perfect Hashing: Upper and Lower Bounds
SIAM Journal on Computing
Are multiport memories physically feasible?
ACM SIGARCH Computer Architecture News - Special issue on input/output in parallel computer systems
Journal of the ACM (JACM)
Smart Memories: a modular reconfigurable architecture
Proceedings of the 27th annual international symposium on Computer architecture
A generic architecture for on-chip packet-switched interconnections
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Parallel hashing: an efficient implementation of shared memory
Journal of the ACM (JACM)
Solving Fundamental Problems on Sparse-Meshes
IEEE Transactions on Parallel and Distributed Systems
Parallel Computer Architecture: A Hardware/Software Approach
Parallel Computer Architecture: A Hardware/Software Approach
Practical Pram Programming
Architectural differences of efficient sequential and parallel computers
Journal of Systems Architecture: the EUROMICRO Journal
Parallelism in random access machines
STOC '78 Proceedings of the tenth annual ACM symposium on Theory of computing
Networks on Silicon: Combining Best-Effort and Guaranteed Services
Proceedings of the conference on Design, automation and test in Europe
A Network on Chip Architecture and Design Methodology
ISVLSI '02 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
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A network on chip (NOC) scheme relying on reuse of existing intellectual property blocks and a unified communication solution has been proposed for solving architectural and design productivity problems of future systems on chips. A NOC consists of a set of heterogeneous computing and storage resources that are connected to each other via a standardized communication network. A heterogeneous structure is suitable for application specific computing, but not for high-speed general purpose computing that is increasingly used in devices that will be powered by NOCs. General purpose functionality can, however, be provided by dedicating the whole chip or a special area on a heterogeneous NOC, called region, for a homogeneous general purpose computing engine. Unfortunately the architectures proposed for NOCs and on-chip parallel computers feature poor performance and portability, or are difficult to program in general purpose computing due to limited communication bandwidth, inability to eliminate delays caused by the latency of the network, high communication overheads, and poor models of parallel computing. In this chapter we will discuss the problems and solutions of implementing an efficient single chip general purpose parallel computing engine. We will also describe our ECLIPSE architecture that can be used either as a truly scalable, high-speed, single chip parallel computer or as a NOC region responsible of general-purpose computation.