Dynamic Perfect Hashing: Upper and Lower Bounds
SIAM Journal on Computing
A generic architecture for on-chip packet-switched interconnections
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Practical Pram Programming
Parallelism in random access machines
STOC '78 Proceedings of the tenth annual ACM symposium on Theory of computing
A Network on Chip Architecture and Design Methodology
ISVLSI '02 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
A design methodology for NOC-based systems
Networks on chip
A parallel computer as a NOC region
Networks on chip
A scalable single-chip multi-processor architecture with on-chip RTOS kernel
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Synthesis and verification
OCCN: A Network-On-Chip Modeling and Simulation Framework
Proceedings of the conference on Design, automation and test in Europe - Volume 3
Packetization and routing analysis of on-chip multiprocessor networks
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Networks on chip
OCCN: a NoC modeling framework for design exploration
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Networks on chip
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
HERMES: an infrastructure for low area overhead packet-switching networks on chip
Integration, the VLSI Journal - Special issue: Networks on chip and reconfigurable fabrics
Cooperative multithreading on 3mbedded multiprocessor architectures enables energy-scalable design
Proceedings of the 42nd annual Design Automation Conference
Simulation and analysis of network on chip architectures: ring, spidergon and 2D mesh
Proceedings of the conference on Design, automation and test in Europe: Designers' forum
A survey of research and practices of Network-on-chip
ACM Computing Surveys (CSUR)
A design methodology for application-specific networks-on-chip
ACM Transactions on Embedded Computing Systems (TECS)
Cache coherency communication cost in a NoC-based MPSoC platform
Proceedings of the 20th annual conference on Integrated circuits and systems design
A predictive NoC architecture for vision systems dedicated to image analysis
EURASIP Journal on Embedded Systems
Advances in c-based parallel design of MP-SOCs
SMO'06 Proceedings of the 6th WSEAS International Conference on Simulation, Modelling and Optimization
Configurable emulated shared memory architecture for general purpose MP-SOCs and NOC regions
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Outline of RISC-based core for multiprocessor on chip architecture supporting moving threads
CompSysTech '09 Proceedings of the International Conference on Computer Systems and Technologies and Workshop for PhD Students in Computing
MVTsim: software simulator for multicore on chip parallel computer architectures
CompSysTech '09 Proceedings of the International Conference on Computer Systems and Technologies and Workshop for PhD Students in Computing
Towards programming on the moving threads architecture
Proceedings of the 11th International Conference on Computer Systems and Technologies and Workshop for PhD Students in Computing on International Conference on Computer Systems and Technologies
Microprocessors & Microsystems
Exploring memory organization in virtual MP-SoC platforms
SBCCI '10 Proceedings of the 23rd symposium on Integrated circuits and system design
Reducing the associativity and size of step caches in CRCW operation
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
A NoC-based hybrid message-passing/shared-memory approach to CMP design
Microprocessors & Microsystems
Performance comparison of some shared memory organizations for 2D mesh-like NOCs
Microprocessors & Microsystems
Parallel programming models for a multiprocessor SoC platform applied to networking and multimedia
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A layout for sparse cube-connected-cycles network
Proceedings of the 12th International Conference on Computer Systems and Technologies
RISC-based moving threads multicore architecture
Proceedings of the 12th International Conference on Computer Systems and Technologies
Dynamic clustering for distinct parallel programming models on NoC-based MPSoCs
Proceedings of the 4th International Workshop on Network on Chip Architectures
Preliminary analysis of feasible benchmark problems for the hydrid PRAM/NUMA REPLICA architecture
Proceedings of the 13th International Conference on Computer Systems and Technologies
Exploring resource mapping policies for dynamic clustering on NoC-based MPSoCs
Proceedings of the Conference on Design, Automation and Test in Europe
Proceedings of the 14th International Conference on Computer Systems and Technologies
Power and Latency Optimized Deadlock-Free Routing Algorithm on Irregular 2D Mesh NoC using LBDRe
International Journal of Embedded and Real-Time Communication Systems
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The Eclipse network-on-a-chip architecture uses a sophisticated parallel programming model, realized through multithreaded processors, interleaved memory modules, and a high-capacity interconnection network to support system-on-a-chip designs.