Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
Journal of Computer and System Sciences
The Stanford Dash Multiprocessor
Computer
An introduction to parallel algorithms
An introduction to parallel algorithms
LogP: towards a realistic model of parallel computation
PPOPP '93 Proceedings of the fourth ACM SIGPLAN symposium on Principles and practice of parallel programming
Dynamic Perfect Hashing: Upper and Lower Bounds
SIAM Journal on Computing
Are multiport memories physically feasible?
ACM SIGARCH Computer Architecture News - Special issue on input/output in parallel computer systems
Solving Fundamental Problems on Sparse-Meshes
IEEE Transactions on Parallel and Distributed Systems
Parallel Computer Architecture: A Hardware/Software Approach
Parallel Computer Architecture: A Hardware/Software Approach
Practical Pram Programming
Simulation-based Comparison of Hash Functions for Emulated Shared Memory
PARLE '93 Proceedings of the 5th International PARLE Conference on Parallel Architectures and Languages Europe
Parallelism in random access machines
STOC '78 Proceedings of the tenth annual ACM symposium on Theory of computing
A Network on Chip Architecture and Design Methodology
ISVLSI '02 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
Networks on chip
Memory-aware NoC exploration and design
Proceedings of the conference on Design, automation and test in Europe
Cm*: a modular, multi-microprocessor
AFIPS '77 Proceedings of the June 13-16, 1977, national computer conference
Memory Systems: Cache, DRAM, Disk
Memory Systems: Cache, DRAM, Disk
Toward realizing a PRAM-on-a-chip vision
Euro-Par'07 Proceedings of the 2007 conference on Parallel processing
A Low-Latency and Memory-Efficient On-chip Network
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
A Network Congestion-Aware Memory Controller
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
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While the research community has already studied a considerable amount of techniques related to achieving high bandwidth, good reliability, low power consumption, certain quality of service in communication on networks on chip (NOC) especially with artificial communication patterns, a little attention has paid to the effects of memory organizations to performance of computing engines employing NOCs with real parallel workloads. In this paper we compare the performance of some shared memory organizations for chip multiprocessors (CMP) employing advanced homogeneous 2D-mesh-like NOCs and making use of emulated shared memory and non-uniform memory access models. The evaluated techniques range from applying different hashing functions to elimination methods of speed difference between processing resources and memories, and from access methods to latency hiding and concurrent memory access support techniques. Tests are performed on our CMP/NOC framework with simple but real parallel programs that can be directly used as building blocks of larger explicitly parallel applications.