A scalable single-chip multi-processor architecture with on-chip RTOS kernel

Authors:
B. D. Theelen;A. C. Verschueren;V. V. Reyes Suárez;M. P. J. Stevens;A. Nuñez
Affiliations:
Information and Communication Systems Group, Faculty of Electrical Engineering, Eindhoven University of Technology, P.O. Box 513, 5600 MB Eindhoven, The Netherlands;SafeNet B.V., P.O. Box 22, 5260 AA Vught, The Netherlands;Applied Microelectronics Research Institute, University of Las Palmas de Gran Canaria, 35017 Las Palmas, Canary Islands, Spain;Information and Communication Systems Group, Faculty of Electrical Engineering, Eindhoven University of Technology, P.O. Box 513, 5600 MB Eindhoven, The Netherlands;Applied Microelectronics Research Institute, University of Las Palmas de Gran Canaria, 35017 Las Palmas, Canary Islands, Spain
Venue:
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Synthesis and verification
Year:
2003

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Abstract

Now that system-on-chip technology is emerging, single-chip multi-processors are becoming feasible. A key problem of designing such systems is the complexity of their on-chip interconnects and memory architecture. It is furthermore unclear at what level software should be integrated. An example of a single-chip multi-processor for real-time (networked) embedded systems is the multi-microprocessor (MµP). Its architecture consists of a scalable number of identical master processors and a configurable set of shared co-processors. Additionally, an on-chip real-time operating system kernel is included to support transparent multi-tasking over the set of master processors. In this paper, we explore the main design issues of the architecture platform on which the MµP is based. In addition, synthesis results are presented for a lightweight configuration of this architecture platform.