A scalable single-chip multi-processor architecture with on-chip RTOS kernel
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Synthesis and verification
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The 'IDaSS' CAD tool [1, 2] maintains an Object-Oriented data structure to specify and simulate digital hardware. This paper gives a global overview of the methods and algorithms which are used to convert this data structure into a standard HDL textual equivalent. Total control over the generated text(s) is achieved by using a rule base which defines how different parts of the data structure are to be written out. This rule base includes special constructs for identifier conversion, name scoping, expression optimisation, data type semantics mapping and multiple file generation. The two separate stages of the conversion (data structure 'decoration' and text generation) are described. Results generated by the (Compass) VHDL and Verilog rule bases, each containing well over 1000 rules, are shown.