Highly concurrent scalar processing
ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
A VLIW architecture for a trace scheduling compiler
ASPLOS II Proceedings of the second international conference on Architectual support for programming languages and operating systems
Speculative disambiguation: a compilation technique for dynamic memory disambiguation
ISCA '94 Proceedings of the 21st annual international symposium on Computer architecture
Trace Scheduling: A Technique for Global Microcode Compaction
IEEE Transactions on Computers
Instruction Set Extensions for MPEG-4 Video
Journal of VLSI Signal Processing Systems - Special issue on implementation of MPEG-4 multimedia codecs
Multimedia Execution Hardware Accelerator
Journal of VLSI Signal Processing Systems - Parallel VLSI architectures for image and video processing
Viper: A Multiprocessor SOC for Advanced Set-Top Box and Digital TV Systems
IEEE Design & Test
Imagine: Media Processing with Streams
IEEE Micro
Measuring the Performance of Multimedia Instruction Sets
IEEE Transactions on Computers
Microcoded Reconfigurable Embedded Processors: Current Developments
Embedded Processor Design Challenges: Systems, Architectures, Modeling, and Simulation - SAMOS
Microcoded reconfigurable embedded processors: current developments
Embedded processor design challenges
An Approach for Quantitative Analysis of Application-Specific Dataflow Architectures
ASAP '97 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors
Architectural approaches for video compression
ASAP '97 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors
Inter-Cluster Communication Models for Clustered VLIW Processors
HPCA '03 Proceedings of the 9th International Symposium on High-Performance Computer Architecture
Cluster assignment of global values for clustered VLIW processors
Proceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systems
A scalable single-chip multi-processor architecture with on-chip RTOS kernel
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Synthesis and verification
Model-Based Exploration of the Design Space for Heterogeneous Systems on Chip
Journal of VLSI Signal Processing Systems
Motion estimation performance of the TM3270 processor
Proceedings of the 2005 ACM symposium on Applied computing
The TM3270 Media-Processor Data Cache
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Proceedings of the 38th annual IEEE/ACM International Symposium on Microarchitecture
Journal of Visual Communication and Image Representation
Cache aware mapping of streaming applications on a multiprocessor system-on-chip
Proceedings of the conference on Design, automation and test in Europe
Improving TriMedia cache performance by profile guided code reordering
SAMOS'07 Proceedings of the 7th international conference on Embedded computer systems: architectures, modeling, and simulation
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TM-1 is the first in a family of programmable multimedia processor from the Trimedia division of Philips Semiconductors. This ``C'' programmable processor has a high performance VLIW-CPU core with video and audio peripheral units designed to support the popular multimedia applications. TM-1 is designed to concurrently process video, audio, graphics, and communication data. The VLIW-CPU core is capable of executing a maximum of twenty seven operations per cycle, and the sustained execution rate is about five operations per cycle for the tuned applications. The audio unit easily handles different audio formats including the 16-bit stereo data. The video unit is capable of processing different YUV and RGB pixel formats with horizontal and vertical scaling and color space conversion. TM-1 applications can range from low-cost, stand alone systems such as video phones to programmable, multipurpose plug-in cards for traditional computers.