VLSI array processors
IEEE Micro
VIS Speeds New Media Processing
IEEE Micro
Architectural approaches for video compression
ASAP '97 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors
Improving Performance for Software MPEG Players
COMPCON '96 Proceedings of the 41st IEEE International Computer Conference
An Architectural Overview of the Programmable Multimedia Processor, TM-1
COMPCON '96 Proceedings of the 41st IEEE International Computer Conference
An MPEG-2 Encoder Architecture Based on a Single-Chip Dedicated LSI with a Control MPU
ICASSP '97 Proceedings of the 1997 IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP '97) -Volume 1 - Volume 1
The MPEG-4 video standard verification model
IEEE Transactions on Circuits and Systems for Video Technology
IEEE Transactions on Circuits and Systems for Video Technology
System-Level Power Optimization of Video Codecs on Embedded Cores: A Systematic Approach
Journal of VLSI Signal Processing Systems - Special issue on future directions in the design and implementations of DSP systems
Vlsi Array Architectures for Pyramid Vector Quantization
Journal of VLSI Signal Processing Systems - Special issue on future directions in the design and implementations of DSP systems
Multimedia Signal Processors: An Architectural Platform with Algorithmic Compilation
Journal of VLSI Signal Processing Systems - special issue on multimedia signal processing
An efficient video decoder design for MPEG-2 MP@ML
ASAP '97 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors
ASAP '97 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors
Architectural approaches for video compression
ASAP '97 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors
VLSI Architecture for Motion Estimation using the Block-Matching Algorithm
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Highly Scalable Parallel Parametrizable Architecture of the Motion Estimator
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Efficient Implementations of Mobile Video Computations on Domain-Specific Reconfigurable Arrays
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Compact FPGA-based systolic array architecture suitable for vision systems
International Journal of High Performance Systems Architecture
Journal of Signal Processing Systems
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An overview on architectures for implementations of current video compression schemes is given. Dedicated as well as programmable approaches are discussed. Examples for dedicated function-specific implementations include architectures for DCT and block matching. For programmable video signal processors, a number of architectural measures to increase video compression performance are reviewed. Actual implementations of video compression schemes typically employ a variety of different architectural approaches. The detailed mix of approaches depends on the targeted application spectrum.