Conception and design of a RISC CPU for the use as embedded controller within a parallel multimedia architecture

Authors:
S. Dogimont;M. Gumm;F. Mombers;D. Mlynek;A. Torielli
Affiliations:
-;-;-;-;-
Venue:
ASAP '97 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors
Year:
1997

Citing 5
Cited 0

Computer architecture: a quantitative approach

Computer architecture: a quantitative approach
Motion Estimation Algorithms for Video Compression

Motion Estimation Algorithms for Video Compression
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MMX Technology Extension to the Intel Architecture

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Architectural approaches for video compression

ASAP '97 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors

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Abstract

In this paper, the problem of defining a high performance control structure for a parallel motion estimation architecture for MPEG2 coding is addressed. Various design and architecture choices are discussed and the final architecture is described. It represents a combined MIMD-SIMD approach which is based on a small but efficient ASIP with subword parallelism.