Multimedia Signal Processors: An Architectural Platform with Algorithmic Compilation

Authors:
Yen-Kuang Chen;S. Y. Kung
Affiliations:
Department of Electrical Engineering, Princeton University, Princeton, NJ 08544;Department of Electrical Engineering, Princeton University, Princeton, NJ 08544
Venue:
Journal of VLSI Signal Processing Systems - special issue on multimedia signal processing
Year:
1998

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Abstract

Novel algorithmic features of multimediaapplications and advances in VLSI technologies are driving forcesbehind the new multimedia signal processors. We propose anarchitecture platform which could provide high performance andflexibility, and would require less external I/O and memory access.It is comprised of array processors to be used as thehardware accelerator and RISC cores to be used as the basisof the programmable processor. It is a hierarchical and scalablearchitecture style which facilitates the hardware-software codesignof multimedia signal processing circuits and systems. While somecontrol-intensive functions can be implemented using programmableCPUs, other computation-intensive functions can rely onhardware accelerators.To compile multimedia algorithms, we also present an operationplacement and scheduling scheme suitable for the proposedarchitectural platform. Our scheme addresses data reusability andexploits local communication in order to avoid thememory/communication bandwidth bottleneck, which leads to fasterprogram execution. Our method shows a promising performance: alinear speed-up of 16 times can be achieved for the block-matchingmotion estimation algorithm and the true motion tracking algorithm,which have formed many multimedia applications (e.g., MPEG-2 andMPEG-4).