Life span strategy—a compiler-based approach to cache coherence
ICS '92 Proceedings of the 6th international conference on Supercomputing
Cache coherence using local knowledge
Proceedings of the 1993 ACM/IEEE conference on Supercomputing
The MIT Alewife machine: architecture and performance
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
ISCA '96 Proceedings of the 23rd annual international symposium on Computer architecture
Hardware and compiler support for cache coherence in large-scale shared-memory multiprocessors
Hardware and compiler support for cache coherence in large-scale shared-memory multiprocessors
Multimedia Signal Processors: An Architectural Platform with Algorithmic Compilation
Journal of VLSI Signal Processing Systems - special issue on multimedia signal processing
A Compiler-Directed Cache Coherence Scheme Using Data Prefetching
IPPS '97 Proceedings of the 11th International Symposium on Parallel Processing
An Integrated Framework for Compiler-Directed Cache Coherence and Data Prefetching
LCPC '98 Proceedings of the 11th International Workshop on Languages and Compilers for Parallel Computing
A Web Proxy Cache Coherency and Replacement Approach
WI '01 Proceedings of the First Asia-Pacific Conference on Web Intelligence: Research and Development
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The performance of large-scale shared-memory multiprocessors can be greatly improved if they can cache remote shared data in the private caches of the processors. However, maintaining cache coherence for such systems remains a challenge. Although hardware directory schemes give good performance, they might be too complicated and expensive for large-scale multiprocessors. This tutorial article provides a comprehensive guide of an alternative approach, called compiler-directed cache coherence techniques. Compiler-directed techniques maintain coherence of caches locally by individual processors, eliminating the need for directory hardware and interprocessor communication. We survey the state of the art software and hardware compiler-directed techniques and discuss the basic concepts and issues related to the topic. We also demonstrate the feasibility and performance of compiler-directed cache coherence by presenting a case study of the Two-Phase Invalidation scheme.