An architecture for the direct execution of the Forth programming language

Authors:
John R. Hayes;Martin E. Fraeman;Robert L. Williams;Thomas Zaremba
Affiliations:
Johns Hopkins Univ., Baltimore, MD;Johns Hopkins Univ., Baltimore, MD;Johns Hopkins Univ., Baltimore, MD;Johns Hopkins Univ., Baltimore, MD
Venue:
ASPLOS II Proceedings of the second international conference on Architectual support for programming languages and operating systems
Year:
1987

Citing 3
Cited 4

Reduced instruction set computers

Communications of the ACM - Special section on computer architecture
High-speed top-of-stack scheme for VLSI processor: a management algorithm and its analysis

ISCA '85 Proceedings of the 12th annual international symposium on Computer architecture
Threaded code

Communications of the ACM

Structuring an instruction cache

ACM SIGARCH Computer Architecture News
The trap as a control flow mechanism

MICRO 21 Proceedings of the 21st annual workshop on Microprogramming and microarchitecture
Stack caching for interpreters

PLDI '95 Proceedings of the ACM SIGPLAN 1995 conference on Programming language design and implementation
Multimedia Signal Processors: An Architectural Platform with Algorithmic Compilation

Journal of VLSI Signal Processing Systems - special issue on multimedia signal processing

Quantified Score

Hi-index	0.00

Visualization

Abstract

We have developed a simple direct execution architecture for a 32 bit Forth microprocessor. The processor can directly access a linear address space of over 4 gigawords. Two instruction types are defined; a subroutine call, and a user defined microcode instruction. On-chip stack caches allow most Forth primitives to execute in a single cycle.