Bulldog: a compiler for VLSI architectures
Bulldog: a compiler for VLSI architectures
Some experiments in global microcode compaction
MICRO 18 Proceedings of the 18th annual workshop on Microprogramming
An architecture for the direct execution of the Forth programming language
ASPLOS II Proceedings of the second international conference on Architectual support for programming languages and operating systems
High-speed top-of-stack scheme for VLSI processor: a management algorithm and its analysis
ISCA '85 Proceedings of the 12th annual international symposium on Computer architecture
An algorithm for global compaction of horizontal microprograms
ACM SIGMICRO Newsletter
Computer Structures: Principles and Examples
Computer Structures: Principles and Examples
Considerations for local compaction of nanocode for the nanodata QM-1
MICRO 14 Proceedings of the 14th annual workshop on Microprogramming
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In this paper we show how traditional hardware trap handlers can be generalized into an efficient vehicle for conditional branches. These ideas are being used in a VLSI processor under design.Conditional branches are often a major bottleneck in scheduling microinstructions on a horizontally microcoded machine. Several tests and conditional branches are frequently ready for scheduling simultaneously, but only one test and branch is possible in a given cycle.The trap facility is traditionally treated as an interrupt scheme for the notification of exceptional conditions. In this paper we study how the role of the trap mechanism may be expanded to include the parallel evaluation of arbitrary user-specified tests, and the concomitant performance benefits.