ACM SIGARCH Computer Architecture News
High-performance computer architecture
High-performance computer architecture
An architecture for the direct execution of the Forth programming language
ASPLOS II Proceedings of the second international conference on Architectual support for programming languages and operating systems
CLIPPER 32-bit microprocessor: user's manual
CLIPPER 32-bit microprocessor: user's manual
ACM Computing Surveys (CSUR)
A reduced register file for RISC architectures
ACM SIGARCH Computer Architecture News
Some innovations in computer architecture
ACM SIGARCH Computer Architecture News
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Structuring an instruction cache to take advantage of known patterns of access reduces its complexity and space requirements and enhances its performance. Two changes are necessary: 1) Caching a program's instructions in packets simplifies the cache's address mechanism and reduces the number of accesses per run. 2) Replacing only those packets which are not anticipating a return reduces the number of cache misses. These changes require only minor modifications to existing cache designs, yet yield immediate benefits in reduced cost and increased performance.