Low-Power Multimedia RISC

Authors:
Kouhei Nadehara;Ichiro Kuroda;Masayuki Daito;Takashi Nakayama
Affiliations:
-;-;-;-
Venue:
IEEE Micro
Year:
1995

Citing 2
Cited 7

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Computer organization & design: the hardware/software interface
Accelerating Multimedia with Enhanced Microprocessors

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An Algorithm-Hardware-System Approach to VLIW Multimedia Processors

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Multimedia Signal Processors: An Architectural Platform with Algorithmic Compilation

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MPEG-2 AAC 5.1-Channel Decoder Software for a Low-Power Embedded RISC Microprocessor

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V830R/AV: Embedded Multimedia Superscalar RISC Processor

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Architectural approaches for video compression

ASAP '97 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors
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WSEAS Transactions on Circuits and Systems
A survey of programmable and dedicated approaches in VLSI architecture design for real-time video processing

ICC'08 Proceedings of the 12th WSEAS international conference on Circuits

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Abstract

The V830, high-performance, low-power RISC microprocessor with signal processing enhancements is designed for low-cost multimedia equipment. It includes special instructions that improve signal-processing performance such as fast multiply/multiply-accumulate instructions, saturated arithmetic instructions, and conditional branch instructions with prediction.Some basic benchmarks show the signal-processing performance of this processor is comparable to that of the latest fixed-point DSPs.